Multi-microprocessor computer systems are frequently used for controlling industrial processes and many kinds of complex system operations. Such computer systems are typically master/slave systems wherein one microprocessor acts as the master which provides overall system control and bus arbitration and the other microprocessors act as responsive slaves for controlling specific functions. Each slave board contains its own control program and system components such that, except for data logging or setpoint changes in a database, it is able to function as a stand alone, single loop controller distributing the work load from one microprocessor to several microprocessors as necessary. This capability therefore allows for a modular development of a particular industrial system or project or alternatively, the simultaneous operation of several different systems or projects. In such systems, the flexibility of a slave board and how it may be utilized is restricted by the nature of the system, as being either hardware-dependent or software-dependent. In a hardware dependent system, the slave board closest to one end of the card cage has a higher priority than a slave card further away from that end of the card cage and gets most of the bus attention to the disadvantage of the slave card at the end of the priority chain which may have severe difficulty in obtaining required bus time. In a variation of the hardware dependent system, the slave is permitted to temporarily take control of the bus while freezing the master. However, this variation allows only one master and one slave per bus and should the slave need the bus frequently, the master may experience repercussions from the frequent interruptions. It is an advantage of hardware dependent systems, that since all bus arbitration is done in hardware, the programmer is freed from having to develop sophisticated master/slave bus protocol software, but a major disadvantage is that a particular manufacturer's slave boards will not work with those of another manufacturer.
The software dependent systems are characterized by the use of "windowing" techniques wherein a portion of the read-and-write memory, hereinafter referred to as the RAM, is allocated common to both the slave and the master. In one technique, the allocated RAM is part of the RAM used by the slave. The central processing unit or "CPU" of the master stops the slave CPU and then transfers a block of information into the slave's RAM area. The slave is then released and if its memory has been modified, the slave moves the new information block to an area of RAM not accessible by the master CPU. In a second technique, a dual part RAM chip is used as the bus interface, acting as a bus buffer and data transfer mechanism controlled by the slave. This technique provides maximum flexibility since all transactions take place via software but the software protocol is very involved to such degree that it is best written by the manufacturer and then purchased as a software routine to be added to a program. A further disadvantage evolves from the operating system of a microprocessor control, hereinafter referred to as "CP/M" , in that there is a limited memory or RAM "window" in the normal memory map addresses which is accessible to a user for programs.
In either of those prior systems, it is not possible to load a program onto the slave card without assistance from the CPU and a considerable collection of specialized development equipment. To run any application program, it is required that the program first be stored in some kind of read-only-memory or ROM. Accordingly, such systems cannot handle dramatically different application program philosophies without changing either the hardware or reprogramming the read-only-memory by using external equipment such as a microprocessor development station and ROM programmers. Furthermore, to use a program on a master CPU requires another program for downloading a command or execute file and such serial downloading is very time consuming, typically several minutes.
Representative systems in the prior art which make evident these limitations are illustrated in U.S. Pat. Nos. 4,459,655 and 4,700,292 which disclose computer systems comprising master and slave microprocessors wherein external equipment such as ROM programmers, proprietary bus structures, and microprocessor development stations are required it if is desired to run an application program. U.S. Pat. No. 4,675,803 discloses a system with an interconnect processor coupled to a slave processor by a first bus and to an operator station by a second bus. While the slave processor may be reprogrammed by the interconnect, an application program must be stored in the erasable programmable read-only-memory (EPROM) or the non-volatile RAM and cannot be downloaded to the slave. U.S. Pat. No. 4,451,884 discloses a data processing system with a secondary subsystem containing processor and memory facilities separate from those of a primary subsystem and U.S. Pat. No. 4,180,860 discloses a universal module for controlling process instrumentation and including a dual mode microprocessor wherein a microprocessor can exchange data with a host station or a remotely located device.